SYNCHRONIZATION HARDWARE

• Many systems provide hardware support for critical section code.
•  The critical section problem could be solved easily in a single-processor environment if we could disallow interrupts to occur while a shared variable or resource is being modified.
• In this manner, we could be sure that the current sequence of instructions would be allowed to execute in order without pre-emption. Unfortunately, this solution is not feasible in a multiprocessor environment.
• Disabling interrupt on a multiprocessor environment can be time consuming as the message is passed to all the processors.
• This message transmission lag, delays entry of threads into critical section and the system efficiency decreases.