COMPUTER ARCHITECTURE NOVEMBER 2021 PSB1B MADRAS UNIVERSITY

 

NOVEMBER 2021                                        PSB1B

 

Time : Three hours                                        Maximum : 75 marks PART A (10 ´ 1 = 10 marks)

Answer any TEN questions.

1.              Define parallel processing.

2.              What is meant by 2’s Complement?

3.              What is a guard bit? What are the ways to truncate the guard bits?

4.              List out the types of interrupts.

5.              What is I/O control method?

6.              Define Page Fault.

7.              What are static and dynamic memories?

8.              What do you mean by associative mapping?

9.              Define instruction pipeline.

10.          What is a Instruction Code?

11.          List out Various branching techniques used  in micro program control unit.

12.          What is meant by Cache memory?

PART B (5 × 5 = 25 marks)

Answer any FIVE questions.

 

13.          Draw the Block diagram of a computer.

14.          What is Memory Interleaving? Explain.

15.          Differentiate        between      programmed        I/O     and interrupt driven I/O.

16.          Construct the Multiplication hardware diagram.

17.          Explain the different types of  hazards  that  can occur in pipeline

18.          Describe the register addressing and relative addressing modes.

19.          Write      the      algorithm       for     restoring      and      non restoring division.

PART C (4 × 10 = 40 marks)

Answer any FOUR questions.

 

20.          Explain         the        floating        point        addition        and subtraction.

21.          Discuss any six ways of improving the cache performance

22.          Describe the methods for dealing with the control hazards.

23.          What is virtual memory? Why is it necessary to implement virtual memory?

24.          What is DMA? Explain the block diagram of DMA. Explain how DMA is used to transfer data from peripherals.

25.          What is BUS? Explain the important Data transfer signals on the PCI bus.

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