PAGING-IMPLEMENTATION OF PAGE TABLE

       Page Table

•  A page table is the data structure used by a virtual memory system in a computer operating system to store the mapping between virtual addresses and physical addresses.
• The MMU contains a page table which is simply an array of entries indexed by page number.
•  Each entry contains some flags (such as the valid bit) and a frame number. 
• The physical address is formed by concatenating the frame number with the offset.

Hardware Implementation of the Page Table
      

• A hardware mechanism is needed to perform the mapping from each instructions effective address to the appropriate physical memory location.
• There must be separate register for each page.
• These may be actual high speed registers or a special area of physical memory.
• The hardware implementation of the page table can be done in several ways.
• In the simplest case,the page table is implemented as a set of dedicated registers.
• These registers should be built with very high speed logic to make the paging address translation efficient.

Hardware support for Paging

• Page table is kept in main memory
• Page Table Base Register(PTBR)points to the page table.
• Page Table Length Register(PTLR)indicates size of the page table.
• In this scheme every data /instruction access requires two memory accesses.One for the page table and one for the data/instruction.
• Problem is with the access time in this case of implementation.

Memory Protection and Sharing

•  Memory protection implemented by associating protection bit with each frame.
• protection bits(access bit) may allow read only,execute  only or other restricted forms of access.
• Every reference physical address is being computed,the protection bits are checked to verify that no writes are being made to a read-only page.
• Specification of access rights in paging systems is useful for pages shared by several processes,but it is of much less value inside the boundaries of a given address space.
• One more bit is generally attached to each entry in the page table, Valid-invalid bit

  1. “valid” indicates that the associated page is in the process  logical address space, and is thus a
         legal page.
  2. “invalid” indicates that the page is not in the process logical  address space.
Paging hardware with TLB

• The CPU's memory management (MMU) stores a cache of recently used mapping from the operating system's page table .
• This is called the Translation Look a side Buffer(TLB).

         LA              PA
CPU------>MMU------->MEMORY
                   |
                   |
                   |
               TLB

TLB:TRANSLATION LOOK A SIDE BUFFER
LA:LOGICAL ADDRESS
PA:PHYSICAL ADDRESS
CPU:CENTRAL PROCESSING UNIT
MMU: MEMORY MANAGEMENT UNIT